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sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 1 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 5 v, 3 a current-mode constant on-time synchronous buck regulator description the sip12107 is a high frequency current-mode constant on-time (cm-cot) synchronous buck regulator with integrated high-side and low-side power mosfets. its power stage is capable of supplying 3 a continuous current at 4 mhz switching frequency. this regulator produces an adjustable output voltage down to 0.6 v from 2.8 v to 5.5 v input rail to accommodate a variety of applications, including computing, consumer electronics, telecom, and industrial. sip12107s cm-cot architecture delivers ultra-fast transient response with mini mum output capacitance and tight ripple regulation at very light load. no esr or external esr network is required for loop stability purpose. the device also incorporates a power saving scheme that significantly increases light load efficiency. the regulator integrates a full protection feature set, including output overvoltage protection (ovp), output under voltage protection (uvp) and thermal shutdown (otp). it also has uvlo for input rail and internal soft-start ramp. the sip12107 is available in lead (pb)-free power enhanced mlp-16l package in 3 mm x 3 mm dimension. features ? halogen-free according to iec 61249-2-21 definition ? 2.8 v to 5.5 v input voltage ? adjustable output voltage down to 0.6 v ? 3 a continuous output current ? programmable switching frequency up to 4 mhz ? 95 % peak efficiency ? supports all ceramic capacito rs no external esr required ? ultrafast transient response ? selectable power saving mo de or force current mode ? 1 % accuracy ? pulse-by-pulse current limit ? scalable with sip12108 - 5a ? fully protected with otp, scp, uvp, ovp ?p good indicator ? compliant to rohs directive 2011/65/eu applications ? notebook computers ? desktop pcs and servers ? handheld devices ? pols for telecom ? consumer electronics ? industrial and automation typical application circuit and package options fig. 1 - typical application circuit for sip12107 v in p g d en av in lx input = 2.8 v to 5.5 v p g nd a g nd power g ood enable v out v out v fb g mo r on auto pwr_ s ave_mode
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 2 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operatio nal sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. absolute maximum ratings electrical parameter conditions limit unit v in reference to p gnd - 0.3 to 6 v av in reference to a gnd - 0.3 to 6 lx reference to p gnd - 0.3 to 6 a gnd to p gnd - 0.3 to + 0.3 all logic inputs reference to a gnd - 0.3 to av in + 0.3 temperature max. operating junction temperature 150 c storage temperature - 65 to 150 power dissipation junction to ambien t thermal impedance (r thja ) 36.3 c/w maximum power dissipation ambient temperature = 25 c 3.4 w ambient temperature = 100 c 1.3 esd protection hbm 2 kv recommended operating range electrical parameter mi nimum typical maximum unit v in 2.8 - 5.5 v av in 2.8 - 5.5 lx - 1 - 5.5 v out 0.6 - 0.85 x v in ambient temperature - 40 to 85 c
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 3 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical specifications parameter symbol test condition unless otherwise specified v in = av in = 3.3 v, t a = - 40 c to 85 c limits unit min. typ. max. power supply power input voltage range v in 2.8 - 5.5 v bias input voltage range av in 2.8 - 5.5 input current iv in_noload device switching, i o = 0 a, r on = 100 k ? , auto = low - 1000 - a shutdown current iv in_shdn en = 0 v - 6 12 av in uvlo threshold av in , u vlo av in rising edge - 2.55 - v av in uvlo hysteresis u vlohys - 300 - mv pwm controller feedback reference v fb t a = 0 c to + 70 c 0.594 0.600 0.606 v t a = - 40 c to + 85 c 0.591 0.600 0.609 v fb input bias current - 2 200 na transconductance -1-ms comp source current -50- a comp sink current -50- switching frequency range guaranted by design 0.2 - 4 mhz minimum on-time guaranted by design - 50 - ns minimum off-time v out = 1.2 v, r on = 100 k ? - 120 - soft start time -1.5-ms integrated mosfets high-side on resistance v in = 3.3 v -56- m ? low-side on resistance -33- fault protections over current limit inducto r valley current - 4.5 - a output ovp threshold v fb with respect to 0.6 v reference -20- % output uvp threshold -- 25- over temperature protection rising temperature - 160 - c hysteresis - 35 - power good power good output threshold v fb rising above 0. 6 v reference - 20 - % v fb falling below 0.6 v reference - - 10 - power good on resistance -30- ? power good delay time -6-s enable threshold logic high level 1.5 - - v logic low level --0.4
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 4 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 functional block diagram fig. 2 - sip12107 functional block diagram ordering information part number package marking (line 2: p/n) sip12107dmp-t1-ge3 qfn33-16l 2107 sip12107db reference board on-time g enerator + - pwm comparator s oft s tart 0.6 v reference a g nd p g ood av in en v fb v in 1,16 v in lx p g nd v in v in 11,12,13 14,15 anti-xcond control 8 6 2 3 zcd + - 0.72 v ov comparator control lo g ic s ection ocp uvlo otp 5 auto 7 g mo ota + - + i s en s e 9 i-v converter i s en s e r on v out 4 10 + - 0.45 v v fb uv comparator pad current mirror format: line 1: dot line 2: p/n line 2: s iliconix logo + e s d s ymbol line 3: factory code + year code + work week code + lot code p/n w11b aa
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 5 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pin configuration fig. 3 - sip12107 pin configuration (top view) pin configuration pin number name function 1v in input supply voltage for power mos. v in = 2.8 v to 5.5 v 2av in input supply voltage for internal circuitry. av in = 2.8 v to 5.5 v 3 en enable pin. enable > 1.5 v 4r on an external resistor between r on and gnd sets the switching on time. 5 auto sets switching mode auto to av in = pwm, auto to gnd = light load mode 6 pgd power good output. open drain. 7 gmo connect to an external rc network for loop compensation and droop function 8a gnd analog ground 9v fb feedback voltage. 0.6 v (typ.) 10 v out v out , output voltage sense connection 11 lx switching output, inductor connection point 12 lx switching output, inductor connection point 13 lx switching output, inductor connection point 14 p gnd power ground 15 p gnd power ground 16 v in input supply voltage for power mos. v in = 2.8 v to 5.5 v lx r on en av in v in v fb v out lx lx auto g mo p g d a g nd v in p g nd p g nd 1 2 3 4 5 6 7 8 12 11 10 9 15 14 13 16 mlpq 3 x 3 - 16l
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 6 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics (v in = 3.3 v, l = 1 h, c = 3 x 22 f, f sw = 1.2 mhz unless noted otherwise) efficiency vs. i out (psm) load regulation: % of v out vs. i out (psm) line regulation 1.2 v out nominal 0 a load (psm) efficiency vs. i out (pwm) load regulation: % of v out vs. i out (pwm) line regulation 1.2 v out at 3 a load (pwm) 1.2 v pwm 1.8 v pwm 1.2 v pwm 1.8 v pwm
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 7 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 f sw variation vs. i out (psm) output ripple psm: 0 a load output ripple pwm: 0 a load f sw variation vs. i out (pwm) output ripple psm: 0 a load output ripple pwm: 3 a load ch1: v out 20 mv/div ch2: lx 2 v/div ch1: v out 20 mv/div ch2: lx 2 v/div
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 8 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 startup psm: 0 a load startup psm: 3 a load startup pwm: 0 a load shutdown psm: 0 a load shutdown psm: 3 a load shutdown pwm: 0 a load v in = 2 v/div v out = 1 v/div p g ood = 2 v/div lx = 2 v/div v in = 2 v/div v out = 1 v/div p g ood = 2 v/div lx = 2 v/div v in = 2 v/div v out = 1 v/div p g ood = 2 v/div lx = 2 v/div v in = 2 v/div v out = 1 v/div p g ood = 2 v/div lx = 2 v/div v in = 2 v/div v out = 1 v/div p g ood = 2 v/div lx = 2 v/div v in = 2 v/div v out = 1 v/div p g ood = 2 v/div lx = 2 v/div
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 9 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 startup pwm: 3 a load load step psm: 0 a to 1.5 a load (undershoot) load step psm: 0 a to 3 a load (undershoot) shutdown pwm: 3 a load load step psm 0 a to 1.5 a load (overshoot) load step psm: 0 a to 3 a load (overshoot) v in = 2 v/div v out = 1 v/div p g ood = 2 v/div lx = 2 v/div v out = 100 mv/div i load = 1 a/div lx = 2 v/div v out = 200 mv/div i load = 5 a/div lx = 2 v/div v in = 2 v/div v out = 1 v/div p g ood = 2 v/div lx = 2 v/div v out = 100 mv/div i load = 1 a/div lx = 2 v/div v out = 200 mv/div i load = 5 a/div lx = 2 v/div
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 10 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 load step pwm: 0 a to 1.5 a load (undershoot) load step pwm: 0 a to 3 a load (undershoot) load step pwm 0 a to 1.5 a load (overshoot) load step pwm 0 a to 3 a load (overshoot) v out = 50 mv/div i load = 2 a/div lx = 2 v/div v out = 100 mv/div i load = 5 a/div lx = 2 v/div v out = 50 mv/div i load = 2 a/div lx = 2 v/div v out = 100 mv/div i load = 5 a/div lx = 2 v/div
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 11 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 operational description device overview sip12107 is a high-efficiency monolithic synchronous buck regulator capable of delivering up to 3 a continuous current. the device has programmable switching frequency up to 4 mhz. the control scheme is based on current-mode constant-on-time architecture, which delivers fast transient response and minimizes exte rnal components. thanks to the internal current ramp i nformation, no high-esr output bulk or virtual esr network is required for the loop stability. this device also incorporates power-saving feature by enabling diode emulation mode and frequency foldback as load decrease. sip12107 has a full set of protection and monitoring features: - over current protection in pulse-by-pulse mode - output over voltage protection - output under voltage protection with device latch - over temperature protection with hysteresis - dedicated enable pin for easy power sequencing - power good open drain output this device is available in mlpq 3 x 3-16l package to deliver high power density and minimize pcb area. power stage sip12107 integrates a high-performance power stage with a ~ 64 m ? p-channel mosfet and a ~ 33 m ? n-channel mosfet. the mosfets are optimized to achieve 95 % efficiency at 2 mhz switching frequency. the power input voltage (v in ) can go up to 5.5 v and down as low as 2.8 v for the power conversion. the logic bias voltage (av in ) ranges from 2.8 v to 5.5 v. pwm control mechanism sip12107 employs a state-of -the-art current-mode cot control mechanism. during steady-state operation, output voltage is compared with internal reference (0.6 v typ.) and the amplified error signal (v comp ) is generated on the comp pin. in the meantime, inductor valley current is sensed, and its slope (i sense ) is converted into a voltage signal (v current ) to be compared with v comp . once v current is lower than v comp , a single shot on-time is generated for a fixed time programmed by the external r on . figure 4 illustrates the basic block diagram for cm-cot architecture and figure 5 demonstrates the basic operational principle: fig. 4 - cm-cot block diagram h g l g h g l g ota - + bandgap v ref v out current mirror l s fet pwm comparator - + - + v in i-amp on-time g enerator v out v in r on control logic & mo s fet driver v comp i s en s e v current
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 12 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 5 - cm-cot operational principle the following equation illustra tes the relation ship between on-time, v in , v out and r on value: once on-time is set, the pseudo constant frequency is then determined by the following equation: loop stability and compensator design due to the nature of current mode control, a simple rc network (type ii compensator) is required between comp and a gnd for loop stability and transient response purpose. general concept of this l oop design is to introduce a single zero through the compensator to determine the crossover fr equency of overall close loop system. the overall loop can be broken down into following segments. output feedback divider transfer function h fb : voltage compensator transfer function g comp (s): modulator transfer function h mod (s): the complete loop transfer function is given by: when: c comp = compensation capacitor r comp = compensation resistor gm = error amplifier transconductance r load = load resistance c o = output capacitor r ds(on) = ls switch resistance r fb1 = feedback resistor connect to lx r fb2 = feedback resistor connect to ground r o = output impedance of error amplifier = 20 m ? av 1 = voltage to current gain = 3 v current v comp pwm fixed on-time v out v in t on = r on x k x , where k = 9.6 x 10 -12 a con s tant s et internally s w = = = d t on 1 v out v in v out v in x r on x k r on x k h fb r fb2 r fb1 x r fb2 ----------------------------- - = g comp (s) r o x 1 + sc comp r comp ?? 1 + sr o c comp ?? ------------------------------------------------------------------------- gm = h mod (s) 1 av 1 x r ds(on) ----------------------------------- x r load x 1 + sc o r esr ?? 1 + sc o r load ?? ------------------------------------------------------------- - = h mod (s) r fb2 r fb1 x r fb2 ----------------------------- - x r o x 1 + sc comp r comp ?? 1 + sr o c comp ?? ------------------------------------------------------------------------- gm x 1 av 1 x r ds(on) ----------------------------------- x r load x 1 + sc o r esr ?? 1 + sc o r load ?? ------------------------------------------------------------- - =
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 13 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power-saving mode operation to further improve efficiency at light-load condition, sip12107 provides a set of in novative implementations to eliminate ls recirculating current and switching losses. the internal zero crossing dete ctor (zcd) monitors lx node voltage to determine when inductor current starts to flow negatively. in power saving mode (psm), as soon as inductor valley current crosses zero, the device first deploys diode emulation mode by turning off ls fet. if load further decreases, switching freq uency is further reduced proportional to load condition to save switching losses while keeping output ripple within tolerance. the switching frequency is set by the controll er to maintain regulation. at zero load this frequency can go as low as hundreds of hz. whenever fixed frequency pwm operation is required over the entire load span, power saving mode feature can be disabled by connecting auto pin to v in or av in . output monitoring and protection features output over-current protection (ocp) sip12107 has pulse-by-pulse over-current limit control. the inductor valley current is mo nitored during ls fet turn-on period through r ds(on) sensing. after a pre -defined time, the valley current is compared with internal threshold (5 a typ.) to determine the threshold for ocp. if monitored current is higher than threshold, hs tu rn-on pulse is skipped and ls fet is kept on until the va lley current returns below ocp limit. in the severe over-current co ndition, pulse-by-pulse current limit eventually triggers output under-voltage protection (uvp), which latches the device off to prevent catastrophic thermal-related failure . uvp is described in the next section. ocp is enabled immediately after av in passes uvlo level. figure 6 illustrates the ocp operation. fig. 6 - over-current protection illustration output under-voltage protection (uvp) uvp is implemented by monitoring output through v fb pin. once the voltage level at v fb is below 0.45 v for more than 20 s, then uvp event is recognized and both hs and ls mosfets are turned off. uvp latches the device off until either av in or en is recycled. uvp is only active after the completion of soft-start sequence. output over-voltage protection (ovp) for ovp implementation, output is monitored through fb pin. after soft-start, if the vo ltage level at fb is above 20 % (typ.), ovp is triggered with hs fet turning off and ls fet turning on immediately to discharge the output. normal operation is resumed once fb voltage drops back to 0.6 v. ovp is active immediately after av in passes uvlo level. over-temperature protection (otp) sip12017 has internal thermal monitor block that turns off both hs and ls fets when ju nction temperature is above 160 c (typ.). a hysteresis of 30 c is implemented, so when junction temperature drops below 130 c, the device restarts by initiating the soft-start sequence again. soft startup sip12107 deploys an intern ally regulated soft-start sequence to realize a monoto nic startup ramp without any output overshoot. once av in is above uvlo level (2.55 v typ.). both the reference and v out will ramp up slowly to regulation in 1 ms (typ.) with the reference going from 0 v to 0.6 v and v out rising monotonically to the programmed output voltage. during soft-start period, ocp is activated. ovp and short-circuit protection are not active until soft-start is complete. i load ocp threshold i inductor gh skipped gh pulse
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 14 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pre-bias startup in case of pre-bias startup, output is monitored through fb pin. if the sensed voltage on fb is higher than the internal reference ramp value, control logic prevents hs and ls fet from switching to avoid negative output voltage spike and excessive current sinking through ls fet. power good (pg) sip12107s power good is an open-drain output. pull pg pin high up to 5 v through a 10k resistor to use this signal. power good window is show n in the below diagram. if voltage level on fb pin is out of this window, pg signal is de-asserted by pulling down to gnd. fig. 7 - pg window and timing diagram design procedure the design process of the sip12107 is quite straight forward. only few passive components such as output capacitors, inductor and r on resistor need to be selected. the following paragraph describes the selection procedure for these peripheral components for a given operating conditions. in the next example the following definitions apply: v inmax. : the highest specified input voltage v inmin. : the minimum effective input voltage subject to voltage drops due to connectors, fuses, switches, and pcb traces there are two values of load current to evaluate - continuous load current and peak load current. continuous load current relates to thermal stress considerations which drive the selection of the inductor and input capacitors. peak load current determines instantaneous component stresses and filtering requir ements such as inductor saturation, output capacitors, and design of the current limit circuit. the following specifications are used in this design: ?v in = 3.3 v 10 % ?v out = 1.2 v 1 % ?f sw = 1 mhz ? load = 3 a maximum setting switching frequency selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. the desired switching frequency, 1 mhz was chosen based on optimizing efficiency while maintaining a small footprint and minimizing component cost. in order to set the design for 1 mhz switching frequency, (r on ) resistor which determine s the on-time (indirectly setting the frequency) needs to be calculated using the following equation. vref (0.6 v) v fb vfb_rising_vth_ov (typ. = 0.725 v) vfb_falling_vth_ov (typ. = 0.675 v) vfb_falling_vth_uv (typ. = 0.525 v) vfb_rising_vth_uv (typ. = 0.575 v) pg pull-high pull-low r on 1 f sw x k ---------------------- 1 1 x 10 6 x 9.6 x 10 -12 -------------------------------------------------------- 105 k ? ? ==
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 15 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 inductor selection in order to determine the indu ctance, the ripple current must first be defined. cost, pcb size , output ripple, and efficiency are all used in the selection process. low inductor values result in smaller size and allo w faster transient performance but create higher ripple current which can reduce efficiency. higher inductor values will re duce the ripple current while compromising the efficiency (higher dcr) and transient response. the ripple current will also set the boundary for power-save operation. the switcher will typically enter power-save mode when the load current decreases to 1/2 of the ripple current. for example, if ripple current is 1 a then power-save operation will typically star t at loads approaching 0.5 a. alternatively, if ripple current is set at 40 % of maximum load current, then power-save w ill start for loads less than ~ 20 % of maximum current. setting the ripple current 20 % to 50 % of the maximum load current provides an optimal trad e-off of the areas mentioned above. the equation for determining inductance is shown next. example in this example, the inductor ripple current is set equal to 30 % of the maximum load curre nt. thus ripple current will be 30 % x 3 a or 0.9 a. to find the minimum inductance needed, use the v in and t on values that correspond to v inmax. plugging numbers into the above equation we get a slightly larger value of 1 h is selected which is a standard value. this will decrease the maximum ripple current by 10 %. note that the inductor must be rated for the maximum dc load current plus 1/2 of the ripple current. the actual ripple current using the chosen 1 h inductor comes out to be. output capacitance calculation the output capacitance is usually chosen to meet transient requirements. a worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capaci tance. if the load release is instantaneou s (load changes from maximum to zero in < 1/f sw s), the output capacitor must absorb all the inductors stored energy. this will approximately cause a peak voltage on the capacitor according to the following equation. assuming a peak voltage v peak of 1.3 v (100 mv rise upon load release), and a 3 a load release, the required capacitance is shown by the next equation. if the load release is relatively slow, the output capacitance can be reduced. using mlcc ceramic capacitors we will use 3 x 22 f or 66 f as the total output capacitance. stability considerations using the output capacitance as a starting point for compensation values. then, taking bode plots and transient response measurements we can fine tune the compensation values. setting the crossover frequenc y to 1/5 of the switching frequency: f 0 = f sw /5 = 1 mhz/5 = 200 khz setting the compensation zero at 1/5 to 1/10 the crossover frequency for the phase boost: setting c c = 1 nf and solve for r c switching frequency variations the switching frequency variation in cot can be mainly attributed to the increase in conduction losses as the load increases. the on time is ide ally constant so the controller must account for losses by reducing the off time which increases the overall duty cycle. hence the f sw will tend to increase with load. in power save mode (psm) the ic will run in pulse skip mode at light loads. as the load increases the f sw will increase until it reaches the nominal set f sw . this transition occurs approximately when the load reach es to 20 % of the full load current. lv in - v out ?? x t on ? i ---------- = l 3.63 v - 1.2 v ?? x 330 x 10 -9 s 0.9 a -------------------------------- 0.891 h = = ? i 3.63 v - 1.2 v ?? x 330 ns 1 h ----------------- - 0.8 a = = c outmin. l x i out + 1 2 -- - x i ripplemax. ?? ?? v peak ?? 2 - v out ?? 2 ------------------------------------------------------------------------- = 2 c outmin. = 1 h x (3 a + 0.5 x (81 a)) 2 (1.3 v) 2 - (1.2 v) 2 = 46.37 f f z = 1 2 x r c x c c = f 0 5 r c = 5 2 x c c x f 0 = 5 2 x 1 nf x 200k = 4k
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 16 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 8 - referenc e board schematic
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 17 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 bill of materials item qty. reference part voltage pcb footprint part number manufacturer 1 4 c1, c2, c3, c4 22 f 16 v sm/c_1210 grm32er71c226me18l murata 2 1 c5 dnp 50 v sm/c_0603 -- 3 2 c7, c13 220 f 25 v 594d-r type 594d227x0016r2t vishay 4 3 c8, c19, c21 0.1 f 50 v sm/c_0603 vj0603y104kxacw1bc vishay 5 3 c9, c10, c11 22 f 6.3 v sm/c_1210 gcm32er70j476ke19l murata 6 3 c12, c29, c30 dnp 6.3 v sm/c_1210 - - 7 2 c14, c20 10 f 16 v sm/c_1206 c1206c106k4ractu taiyo yuden 8 1 c15 0.1 f 50 v sm/c_0402 vj0603y104kxacw1bc vishay 9 1 c16 68 pf 50 v sm/c_0603 vj0402a680jnaaj vishay 10 1 c17 0.1 f 50 v sm/c_0402 vj0402y104kxacw1bc vishay 11 1 c18 68 pf 50 v sm/c_0402 vj0402a680jnaaj vishay 12 1 c23 2.2 f 10 v sm/c_0603 grm188r71a225ke15d murata 13 1 c26 dnp 50 v sm/c_0402 - - 14 1 c27 1 nf 50 v sm/c_0402 vj0402y102kxacw1bc vishay 29 1 l1 1h - ihlp2525 IHLP2525DZER1R0M01 vishay 30 1 q1 - 30 v so-8 si4812bdy vishay 31 1 r1 3r01 200 v c_2512 crcw25123r01fkta vishay 32 4 r2, r3, r5, r9 100k 50 v sm/c_0603 crcw0603100kfkea vishay 33 1 r6 100 50 v sm/c_0402 tnpw0402100rbeed vishay 34 1 r7 5k11 50 v sm/c_0603 crcw06035k11fkea vishay 35 1 r8 0r 50 v sm/c_0402 crcw04020000fkta vishay 36 1 r10 5k11 - sm/c_0603 crcw06035k11fkea - 37 1 r11 100 50 v sm/c_0603 tnpw0402100rbeed vishay 38 1 r12 10k 50 v sm/c_0603 crcw060310k0fkea vishay 39 1 r14 100k 50 v sm/c_0603 crcw0603100kfkea vishay 40 1 r42 2k 50 v sm/c_0603 crcw06032k00fkea vishay 41 1 r43 dnp - sm/c_0805 - 42 1 r44 0r 50 v sm/c_0603 crcw06030000z0ea vishay 43 1 r45 0r 50 v sm/c_0402 crcw04020000fkta vishay 44 1 u1 - - qfn3x3_16 l sip12107 vishay 45 1 j1 v in probe pin pk007-015 lecroy 46 1 j2 lx probe pin pk007-015 lecroy 47 1 j3 v in power connector 575-6 keystone 48 1 j4 v out power connector 575-6 keystone 49 1 j5 v out probe pin pk007-015 lecroy 50 1 j6 v in _gnd power connector 575-6 keystone 51 1 j7 v o _gnd power connector 575-6 keystone 52 1 j8 en control pin 1573-3 keystone 53 1 j9 mode control pin 1573-3 keystone 54 1 j10 pgd probe pin 1573-3 keystone 55 1 j11 step_i_sense probe pin 1573-3 keystone 56 1 j12 ldt sma test connector pk007-015 lecroy 57 1 j13 ch2 test point 1573-3 keystone 58 1 j14 ch1 test point 1573-3 keystone
sip12107 www.vishay.com vishay siliconix s12-0412-rev. b, 20-feb-12 18 document number: 63395 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pcb layout of reference board fig. 9 - top layer fig. 10 - inner layer1 fig. 11 - bottom layer fig. 12 - inner layer2 vishay siliconix maintains worldwide manufactu ring capability. products may be manufact ured at one of seve ral qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63395 .
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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